1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, it relates to a semiconductor device having a conductor film on an insulating film connected to a semiconductor substrate electrically and a method of manufacturing the same.
2. Description of the Prior Art
Electrical connections between the conductor film on the insulating film and the semiconductor substrate are necessary in many semiconductor devices and particularly it is significant on a memory cell portion of a dynamic-type semiconductor memory device. One example of such electrical connections is electrical connections between a capacitor electrode for storing information represented by an electric charge and a drain region of a transistor for reading and writing of information represented by an electric charge.
FIG. 1 is a block diagram showing a whole structure of a dynamic-type semiconductor memory device.
Referring to FIG. 1, the dynamic-type semiconductor memory device comprises an array comprising a plurality of memory cells serving as a memory portion, an X decoder and a Y decoder for selecting its address, and an input/output interface portion comprising a sense amplifier connected to an input/output buffer. A plurality of memory cells serving as a memory portion are connected to each of intersection points of word lines connected to the X decoder and bit lines connected to the Y decoder, these word and bit lines constituting a matrix. The above-mentioned array is thus implemented.
Next, an operation is described. The memory cell at an intersection point of the word line and the bit line is selected, when those lines are selected by the X decoder and the Y decoder in response to a row address signal and a column address signal externally provided, and information is read or written from or to the memory cell through the input/output interface portion comprising the sense amplifier and the input/output buffer.
FIGS. 2A-2C are diagrams showing one example of conventional electrical connections between a conductor film on an insulating film and a semiconductor substrate. The shown example, particularly, is an example of connections on a memory cell portion of a dynamic-type semiconductor memory device. An insulating film 2 is formed on the semiconductor substrate. A window (serving as a connection portion) is formed on the insulating film by a photolithography (FIG. 2A). A polycrystalline silicon film 4 serving as a wire layer is formed on the insulating film (FIG. 2B). At this time, an impurity such as arsenic, phosphorous and boron may be implanted into the polycrystalline silicon film using an electric furnace or an ion implantation method. Then, a resist is applied to a desired position on the polycrystalline silicon layer and a patterning is performed, whereby the wire layer is formed (FIG. 2C).
In the conventional method of electrical connections, a window on the insulating film 2 for connecting the polycrystalline silicon film 4 on the insulating film 2 with a semiconductor substrate 1 must have been formed using a photolithography. Thus, minute processing of the window was difficult. In addition, since the insulating film 2 is usually used as the gate insulating film, a gate insulating film could be badly influenced by impurities in the resist.
A method of electrically connecting the conductor film on the insulating film to the semiconductor substrate other than the above-mentioned method is described in Japanese Patent Laying-Open Gazette No. 175846/1983 and 216447/1986. FIGS. 3A and 3B are diagrams showing the method of electrical connections described in the latter mentioned literature. FIG. 3A is a plan view of an electrically connected portion and FIG. 3B is a sectional view taken along the line A-A' in FIG. 3A. Referring to the figures, connections between a gate 3 formed of the polycrystalline silicon layer and the substrate 1 are made through a wire layer 6 covering a step portion 5. The wire layer 6 is formed by a selective epitaxial growth of silicon. A single crystal layer is formed on silicon of the substrate 1 and a polycrystalline silicon layer is formed on polycrystalline silicon layer of the gate 3.
In the above-mentioned method, there were problems that when the impurity is implanted into the inside of the silicon layer, it is difficult to control it because the silicon layer formed by an epitaxial growth comprises two kinds of the single crystal silicon layer and polycrystalline silicon layer. Also, it is difficult to form a minute contact hole smaller than 0.5.mu. since a portion formed by the selective epitaxial growth, that is, a contact portion is formed using the photolithographic process. It is still further difficult to form a minute contact hole in alignment precisely, so that problems were caused that the above mentioned method is poor in repeatability and it is not suitable for a minute processing.